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Programmable Clock Divider & Delay, DC - 4 GHz

Product Details

Data Sheet

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Product Press Release

Life Cycle Status

Production, Recommended for New Designs

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Eval. PCB Schematic
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Clock Rate (GHz) Function Input Output Phase Jitter (12 K to 20 MHz) Rise / Fall Time (ps) Channel Skew (ps) Power Supply (V)
DC - 4 Clock Divider &
Delay Management
LVPECL, LVDS, CML, CMOS LVPECL 13 fs RMS 90 300 to 1500
Prog. Delay
5 or 3.3


• Programmable Clock Divide by
• Delay Adjustment in Multiples of 1/2
   Clock Cycles or in 60 Steps
    of 20 ps (Typ.)
• -170 dBc/Hz Noise Floor
    @ 100 MHz Output
• Up to 4 GHz Operation with
    800 mVp-p LVPECL Output
• 3.3V Operation (or 5V Operation with
    Optional On-Chip Regulator for
    Best Performance)

Typical Applications

• Basestation Digital Pre-Distortion
    Paths (DPD)
• High Performance Automated Test
    Equipment (ATE)
• Backplane Clock Skew Management
• Phase Coherence of Multiple Clock
• Clock Delay Management to
   Improve Setup & Hold Time Margins
• PCB Signal Flight Time Offset Circuits
• Track and Hold Circuits for ADC/DACs

Functional Diagram


General Description

The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. It is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm SMT QFN package, the clock divider offers a high level of functionality. The device works with 3.3V supply or may be connected to 5V supply and utilize the optional on-chip regulator. This on-chip regulator may be bypassed. Up to 8 addressable HMC988LP3E devices can be used together on the SPI bus. The HMC988LP3E is ideally suited for data converter applications with extremely low phase noise requirements.