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HMC674LP3E

Latched Comparator with RSPECL Output Stage SMT, 10 GHz

Product Details

Data Sheet
Application Notes
Package Layout
Tape & Reel
ECCN: 3A001.a.11.b

Quality & Reliability

Environmental Data Sheet
Qualification Test Reports

Press & Media

Product Press Release

Life Cycle Status

Production, Recommended for New Designs
Analog Input Bandwidth (GHz) Function Deter-
ministic Jitter (ps)		 DC Power Consumption (mW) Vcci, Vcco, Vterm, Vee Power Supply (Vdc) Package
10 Latched Comparator-RSPECL 2 140 +3.3, +3.3, +1.3, -3 LP3

Features

• Propagation Delay: 85 ps
• Overdrive & Slew Rate Dispersion: 10 ps
• Minimum Pulse Width: 60 ps
• Resistor Programmable Hysteresis
• Differential Latch Control
• Active Gain: 48 dB
• Power Dissipation: 140 mW
• RSCML & RSECL Versions Available
• 16 Lead 3x3mm SMT
   Package: 9mm²

Typical Applications

• ATE Applications
• High Speed Instrumentation
• Digital Receiver Systems
• Pulse Spectroscopy
• High Speed Trigger Circuits
• Clock & Data Restoration

Functional Diagram

HMC674LP3E Functional Diagram

General Description

The HMC674LP3E is a SiGe monolithic, ultra fast comparator which features reduced swing PECL output drivers and latch inputs. The comparator supports 10 Gbps operation while providing 85 ps propagation delay and 60 ps minimum pulse width with 0.2 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically 10 ps, making the device ideal for a wide range of applications from ATE to broadband communications.


The reduced swing PECL output stages are designed to directly drive 400 mV into 50 Ohms terminated to +1.3V while maintaining compatibility with other PECL logic families. The HMC674LP3E features high speed latch and programmable hysteresis and may be configured to operate in either latch mode, or as a tracking comparator.