Is the EasyStack™ firmware code for the Xilinx® SP601 evaluation board available?
Yes, the Verilog code is available. Please contact Hittite for more information.
How is the power consumption of the Hittite A/D Converters affected by the input clock (sample) rate?
The Hittite ADC series are designed to scale power consumption nearly linear with sample rate. The graph below is a rough guide but illustrates this point. Many factors will affect power consumption, see Hittite for details.
I recently received the HMCAD1520 evaluation kit (with the Xilinx® SP601). However, I have been unable to start the EasySuite™ software due to the following error: "The loaded FPGA code xxxxx do not support the HMCAD1520 device.
This problem can happen with using outdated firmware for the Xilinx® SP601 motherboard and/or older software of EasySuite™. The solution is to install the latest EasySuite™ version onto the PC and load the new firmware into the Xilinx® SP601.
The firmware files (one common for all product series HMCAD10xx, HMCAD11xx and HMCAD15xx) is located in the directory: ..hittite Microwave CorpEasySuiteHmc1520_sp601_rev118.mcs (or later version)
This file will automatically update the firmware when another product series evaluation board is connected.
For instructions on loading an .mcs file please refer to: EasyStack™_Xilinx® SP601_UserGuide.pdf
The new version Firmware and Software can be downloaded from the product homepage: http://www.hittite.com/products/view.html/view/HMCAD1520
How does one configure the HMCAD1520 evaluation daughter board to accept a clock input from the Xilinx® SP601 motherboard?
The Spartan-6 FPGA has two differential lines that are connected to the Hittite ADC daughterboard via the FMC connector. The EVAL01-HMCAD1520 daughterboard modifications necessary for connecting to the FPGA clock are as follows:
In addition, on the bottom-side of the EVAL01-HMCAD1520, R41 and R42 connects the FPGA_CKP and FPGA_CKN lines to the IO_L14P_0_GCLK19_D9 (pin D9) and IO_L14N_0_GCLK18_C9 (pin C9) lines on the Spartan-6.
Alternatively, R41 and R42 can be removed, and the "CKGEN_CKN" (FPGA pin A10) and "CKGEN_CKP" (FPGA pin C10) can be connected by shorting U2 pins 21 and 10, and pins 22 and 7 (with U2 removed), and mounting zero Ohm resistors R28 and R29.
Unfortunately, this adjustment will only get you access to the FPGA pins.
The clock signal still has to be generated and placed on those pins by the FPGA code. The two clocks that connect to the FPGA on the SP601 are the 27 MHz user-clock (FPGA pin V10) and the 200 MHz sysclk (FPGA differential pins K15 and K16). These frequencies or a down-divided frequency from 27 or 200 MHz can be routed to the FPGA clock output pins.
In addition, the internal PLL can generate 6 different frequencies from these input frequencies. However, the PLL is in use for the EVAL01-HMCAD1520 to generate the 500 MHz LVDS bus clock, so that only frequencies divided down from 500 MHz (i.e. 500 MHz/N) will be available from the PLL on the 5 remaining outputs.
Any clock generation from the FPGA would mean a patch to the existing EasyStack™ FPGA code. The code is available from Hittite upon request.
Does the HMCAD15xx ADC family (HMCAD1520, 1511, 1510) support SDR LVDS output?
No, only DDR LVDS is supported on the HMCAD15xx ADC family. The HMCAD11xx family (HMCAD1100, 1101, 1102) supports both DDR and SDR LVDS outputs.
Are the LVDS output test patterns affected by the setting of the 2’s complement bit?
Yes, the 2’s complement bit will flip the MSB in normal operation and when the test pattern is active.
Is the EasySuite™ software supported under Linux or MAC OS®?
It is possible to use EasySuite™ on Linux and Mac. The Windows® installation file un-wraps a java runtime file (easysuite.jar). This file can be copied to any system with java already installed. The system is developed on CentOS®/RedHat 5.4®, so it is proven on Linux® systems.
For automatic detection of USB devices, install the fxload utility program. The user that runs the software must have read/write access to the /var/lock directory. This can be enabled by running this command as root:
Is there a way to read saved data back into the EasySuite™ tool?
EasySuite™ does not support read-back nor display of old sample-data. However, the stored data-format is standard ASCII, one sample value per line in a .txt file with one .txt file per channel. ASCII makes it very easy to read the channel sampling data into other programs for display and post processing purposes. MATLAB™, Excel and most other programs can read and display the data.
What is the minimum sampling rate for the HMCAD converters?
The minimum sampling rate depends on the part # and, in some case, the number of active channels. See the chart below.
|Hittite Part Number||Minimum Sampling Rate (MSPS)|
|HMCAD1510, HMCAD1511, HMCAD1520||1 Ch||2 Ch||4 Ch|
Is there a summary of the LVDS output modes and data rates for the HMCAD110x and HMCAD15xx data converters?
Yes, please see the following Application note for reference: LVDS Output Modes on the HMCAD15xx & HMCAD11xx ADCs
If a dither circuit is used, what is the appropriate level for the HMCAD1520?
Dither can be most effective when the level is relatively high, but it is important that the dither level is different from the internal reference voltage divided by 2n. For the HMCAD1520, the internal reference is a differential 1V, so a dither level of 1/20 volt works well. (It must NOT be 1/16 or 1/32V according to the requirements above). A high dither level requires that it can be effectively subtracted from the output signal.
What is the memory capacity of the Xilinx® Spartan SP601 evaluation board?
The Xilinx® Spartan SP601 evaluation board contains 8 MB Quad SPI Flash, 16 MB Parallel (BPI) Flash and 128 MB DDR2 Component memory.
Are the Gerber files for the HMCADXXXX evaluation board available?
Yes, the Gerber files are available. Please contact Hittite for more information.
Should the exposed pad, pin 0, be grounded?
The exposed pad is a standard part of QFN packages. It is used for power dissipation reasons on Hittite A/D converters series and should be grounded. Shown below is the top layer for a Hittite A/D converters series evaluation board. Note the copper material underneath the A/D QFN package leading to the larger ground plane.